Clock signals are used by complex sequential digital circuits to synchronize the operation of the circuit and perform its operations in an orderly manner. These signals are periodical signals with known timing. The timing provides the reference at which the state of the digital system is changed. The use of clock signals allows coherent functioning of the entire circuit design. The clock signal may be distributed over the circuit design and used by all storage elements. This is known as single phase clocking strategy. In multiple phase clocking strategy, timing relationships are used between clock phases to relax the timing requirements. Multiple clocks of same frequency separated by a fixed phase difference are generated. This makes the circuit to operate at a frequency N times lower than actual frequency, where N is the number of phases of clock used.
Many techniques have been employed to generate multiphase clock signals. One possible technique is to make a ring oscillator and tap its nodes. A voltage controlled or current controlled differential ring oscillator having multiple stages of delayed differential inverted amplifiers connected in a ring form is used to generate multiphase clock signals having the same phase difference.
However, this technique faces a number of shortcomings. The layout of the circuit has to be made absolutely matched. Even the parasitic capacitances seen at the intermediate node of the ring have to be same. Difference in parasitic capacitances may result in asymmetric waveforms. Moreover, if large number of phases is required, the number of stages needed also increases. When these stages are attempted to match, the parasitic loading in the intermediate nodes increases. This in turn limits the frequency of operation of the oscillator.
Another technique used for generation of multiple phase clock pulses is that of interpolation between two phases (as disclosed by U.S. Pat. No. 6,380,774 to Saeki). A clock control circuit is made comprising of a frequency multiplying interpolator and at least one phase adjusting interpolator as its basic components. The frequency multiplying interpolator includes a plurality of circuits each of which is for outputting signal obtained by internally dividing a phase difference between two signals, for generating a plurality of frequency multiplied clocks, which have phases that differ from one another. Two of such frequency multiplied clocks are input to the phase adjusting interpolator. Multiphase clock signals are then obtained by internally dividing phase difference between these two frequency multiplied clocks.
However, this technique generates phase errors in the interpolated clocks. Any mismatch during the entire process of interpolation may lead to large deviations. If the clock phases have short rise/fall times then the interpolated value deviates from ideal value since the input clocks to the interpolator are in non linear region. If the clock phases have bigger rise/fall times, effects of offsets and noise in the circuit increase.
U.S. Pat. No. 6,809,567 B1 to Kim et al discloses yet another technique for multiple phase clock generation. The technique utilizes a multiple-stage voltage controlled oscillator for generating a plurality of clock phases. These clock phases are then fed to a clock divider circuit. The clock divider circuit includes a modified Johnson counter which generates a plurality of clock phases from each output of voltage controlled oscillator. Each output of the Johnson counter is connected to a separate modified shift register. These shift registers contain D-type flip flops and each flip flop provides a separate clock phase output.
The above mentioned technique is an efficient method of generating multiple phase clock signals. However, the circuitry required for implementation of disclosed technique is very large and extensive.
Therefore there is a need for a system and method that generates multiple clocks of same frequency separated by a fixed and exact phase difference having symmetric waveforms and at the same time which can be implemented using minimal and simple circuitry.